November 21 2020

IAR Embedded Workbench for RISC-V version 1.30.2 (32bit / 64bit)

IAR Embedded Workbench for RISC-V version 1.30.2 (32bit / 64bit)
IAR Embedded Workbench for RISC-V version 1.30.2 | 299.1 mb

Languages: English, 日本語

IAR Systems, the future-proof supplier of software tools and services for embedded development, has extended the complete development toolchain IAR Embedded Workbench for RISC-V with support for trace as implemented by SiFive Insight, the industry's first combined pre-integrated trace and debug solution for the freely-available, open-specification RISC-V ISA.

Release notes for IAR Embedded Workbench for RISC-V version 1.30

Compiler and library optimizations
- New libraries to support and optimize performance for devices without M
- Size-optimized libraries introduced as an option to the already existing speed-optimized versions
- Several compiler optimizations for speed and size
P extension DSP and Packed SIMD
- Support for the draft DSP and Packed SIMD specification, including intrinsic functions to support Andes DSP libraries.
Updated Trace capabilities
- Function profiling makes it possible to see and analyze timing information for the functions in an application
- Code coverage shows the percentage of code that has been executed
- Support for on-chip RAM-buffered Trace
- Enhanced support for SiFive Insight debug solution
- Automatic interrupt vector setup
- Support for automated interrupt vector setup for devices from Andes and GigaDevice
Extended C-STAT coverage for MISRA C:2012 Amendment 1
The Static analysis tool C-STAT has extended its coverage of the MISRA C:2012 Coding Standard and now fully supports MISRA C:2012 Amendment 1. This Amendment adds 14 additional rules to MISRA C:2012 with a focus on security concerns highlighted by the ISO C Secure Guidelines. Several of these address specific issues pertaining to the use of untrustworthy data, a well-known security vulnerability.
New supported devices
The following devices from GigaDevice are now supported: GD32VF103C4T6, GD32VF103C6T6, GD32VF103C8T6, GD32VF103CBT6, GD32VF103R4T6, GD32VF103R6T6, GD32VF103R8T6, GD32VF103RBT6, GD32VF103T4U6, GD32VF103T6U6, GD32VF103T8U6, GD32VF103TBU6, GD32VF103V8T6, GD32VF103VBT6

IAR Embedded Workbench is a complete development toolchain including the highly optimizing IAR C/C++ Compiler and the feature-rich C-SPY Debugger. The software is complemented by native debugging and trace probes. The debug probe I-jet supports on-chip RAM buffered trace, in addition to fast JTAG/cJTAG/DAP debug and is complemented by the powerful trace probe I-jet Trace, which can livestream trace information for code coverage and profiling purposes. The new trace features include an updated trace control and status window that provides developers with full control of all active settings and the live trace status of the application. The C-SPY Debugger will decode trace and calculate coverage and profiling as the application executes, populating the respective windows on the fly. This live update enables developers to monitor everything from the available trace buffer to the number of covered instructions. In addition, function profiling makes it possible to see and analyze timing information for the functions in an application, while code coverage analysis shows the percentage of code that has been executed down to single instruction resolution. These combined capabilities offer a non-intrusive and easy-to-use code optimization tool.

Launched in 2019, IAR Embedded Workbench for RISC-V provides excellent optimization technology, helping developers ensure the application fits the required needs and optimize the utilization of on-board memory. This also enables companies to aggregate value by adding functionality to an existing platform. To ensure code quality, the toolchain includes the static analysis tool C-STAT®, which proves code compliance with specific standards like MISRA C:2004, MISRA C++:2008 and MISRA C:2012, as well as detect defects, bugs, and security vulnerabilities as defined by the Common Weakness Enumeration (CWE) and a subset of CERT C/C++.

The current version of IAR Embedded Workbench for RISC-V provides support for RV32 and RV32E 32-bit RISC-V cores and numerous ISA extensions such as C for compressed instructions, and F and D for single-precision and double-precision floating points. Future releases will enhance debug and trace capabilities following RISC-V standardization efforts. Complementing its strong tools product offering, IAR Systems delivers outstanding technical support from offices around the globe.

Get Started with IAR Embedded Workbench for RISC-V

IAR Systems supplies future-proof software tools and services for embedded development, enabling companies worldwide to create the products of today and the innovations of tomorrow. Since 1983, IAR Systems' solutions have ensured quality, reliability and efficiency in the development of over one million embedded applications. The company is headquartered in Uppsala, Sweden and has sales and support offices all over the world.

Product: IAR Embedded Workbench
Version: for RISC-V version 1.30.2
Supported Architectures: 32bit / 64bit
Website Home Page :

Language: english, 日本語
System Requirements: PC *
Size: 299.1 mb

System requirements

To install and run this version of IAR Embedded Workbench you need:
- A Pentium-compatible PC with Windows 7, Windows 8, Windows 8.1, or Windows 10. Both 32-bit and 64-bit variants of Windows are supported.
- Internet Explorer 8 or higher
- At least 4 Gbyte of RAM, and 10 Gbytes of free disk space.
- Adobe Acrobat Reader to access the product documentation
Third-party debugger drivers, might or might not work depending on their level of support for the Windows version used.
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